1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to a communication transaction control between independently controllable circuit domains within an integrated circuit.
2. Description of the Prior Art
As integrated circuits have increased in complexity, it has become more common to divide such circuits into multiple independently controllable domains. These domains can be independently controllable in the sense that they may be subject to independent power control, independent clocking (asynchronous and/or different speeds), independent resets, independent error recovery (e.g. from speculative processing errors (e.g. see the type of speculative processing described in WO-A-2004/084072, the content of which is incorporated herein in its entirety by reference) or errors due to particle strikes, etc.) or combinations of the above or other control parameters. The separate domains may, for example, contain circuit elements such as a DSP circuit, a general purpose CPU, peripheral interface circuits and the like, which can be selectively powered down when not in use, subject to different clocking speeds, subject to independent reset signals depending upon the circumstances or subject to independent error recovery mechanisms. Whilst such different domains are subject to this independent control, they are also required to communicate with each other via communication transactions and in accordance with predetermined transaction protocols. It is advantageous if the different circuit elements standardise their transaction protocol so as to facilitate design reuse and interoperability. An example of such transaction protocols are the AMBA transaction protocols originated by ARM Limited, Cambridge, England, such as the AHB protocol. Such transaction protocols typically require a predetermined sequence of signals to be generated and responses received by each party until the transaction completes. If one or more of these signals is in someway lost, then the transaction protocol is not complied with and an erroneous operation can occur, e.g. in a severe case an entire communication bus may be locked up due to an incomplete transaction.
One approach to dealing with this problem is to seek to ensure that each circuit taking part in the transaction fully completes every transaction which it has started before being disrupted by any other influence. As an example, a circuit element may defer being powered down or reset until it has completed all of its pending transactions. However, this requirement can introduce significant disadvantageous complexity and/or other performance problems, such as inadvertently delaying a required reset for an indeterminate period of time.
Another problem arises in systems in which different domains are subject to independent error recovery, with errors occurring relatively frequently as part of their expected behaviour. Non-permanent, or soft errors, for example, due to particle strikes, are becoming more frequent. In a desire to run at higher speeds and lower voltages, timing margins are being reduced such that timing errors become relatively frequent. These frequent errors can be handled by building in appropriate recovery mechanisms for the domains in which the errors have occurred. Stopping the propagation of these errors beyond the domain in which they occur and reducing the time lost in recovering from these errors are both desirable aims.